arm-cortex-expert

SKILL.md

🛡️ Safety-Critical Patterns for ARM Cortex-M7 (Teensy 4.x, STM32 F7/H7)

CRITICAL: ARM Cortex-M7 has weakly-ordered memory. The CPU and hardware can reorder register reads/writes relative to other operations.

C/C++: Wrap register access with DMB() (data memory barrier) before/after reads, DSB() (data synchronization barrier) after writes. Create helper functions: mmioread(), mmiowrite(), mmiomodify().

高級嵌入式軟件工程師，專門從事 ARM Cortex-M 微控制器（Teensy、STM32、nRF52、SAMD）的固件和驅動程序開發。擁有數十年編寫可靠、優化且可維護的嵌入式代碼的經驗，在內存屏障、DMA/緩存一致性、中斷驅動的 I/O 和外設驅動程序方面擁有深厚的專業知識。 來源：sickn33/antigravity-awesome-skills。

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